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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>EON</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">EON</h2><p>Bitwise exclusive OR with inverted immediate (unpredicated)</p>
      <p class="aml">Bitwise exclusive OR an inverted immediate with each 64-bit element of the source vector, and destructively place the results in the corresponding elements of the source vector. The immediate is a 64-bit value consisting of a single run of ones or zeros repeating every 2, 4, 8, 16, 32 or 64 bits. This instruction is unpredicated.</p>
    <p>
        This is a pseudo-instruction of
        <a href="eor_z_zi.html">EOR (immediate)</a>.
        This means:
      </p><ul><li>
          The encodings in this description are named to match the encodings of
          <a href="eor_z_zi.html">EOR (immediate)</a>.
        </li><li>
            The assembler syntax is used only for assembly, and is not used on disassembly.
          </li><li>The description of <a href="eor_z_zi.html">EOR (immediate)</a> gives the operational pseudocode, any <span class="arm-defined-word">constrained unpredictable</span> behavior, and any operational information for this instruction.</li></ul>
    <p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">1</td><td class="l">0</td><td>0</td><td>0</td><td class="r">0</td><td colspan="13" class="lr">imm13</td><td colspan="5" class="lr">Zdn</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="EON_eor_z_zi_"/><p class="asm-code">EON     <a href="#sa_zdn" title="Source and destination scalable vector register (field &quot;Zdn&quot;)">&lt;Zdn&gt;</a>.<a href="#sa_t" title="Size specifier (field &quot;imm13&lt;12&gt;:imm13&lt;5:0&gt;&quot;) [B,D,H,S]">&lt;T&gt;</a>, <a href="#sa_zdn" title="Source and destination scalable vector register (field &quot;Zdn&quot;)">&lt;Zdn&gt;</a>.<a href="#sa_t" title="Size specifier (field &quot;imm13&lt;12&gt;:imm13&lt;5:0&gt;&quot;) [B,D,H,S]">&lt;T&gt;</a>, #<a href="#sa_const" title="64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits (field &quot;imm13&quot;)">&lt;const&gt;</a></p><p class="equivto">
      is equivalent to
    </p>
          <p class="asm-code"><a href="eor_z_zi.html#eor_z_zi_">EOR</a> <a href="#sa_zdn" title="Source and destination scalable vector register (field &quot;Zdn&quot;)">&lt;Zdn&gt;</a>.<a href="#sa_t" title="Size specifier (field &quot;imm13&lt;12&gt;:imm13&lt;5:0&gt;&quot;) [B,D,H,S]">&lt;T&gt;</a>, <a href="#sa_zdn" title="Source and destination scalable vector register (field &quot;Zdn&quot;)">&lt;Zdn&gt;</a>.<a href="#sa_t" title="Size specifier (field &quot;imm13&lt;12&gt;:imm13&lt;5:0&gt;&quot;) [B,D,H,S]">&lt;T&gt;</a>, #(-<a href="#sa_const" title="64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits (field &quot;imm13&quot;)">&lt;const&gt;</a> - 1)</p>
          
        </div>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Zdn&gt;</td><td><a id="sa_zdn"/>
        
          <p class="aml">Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;T&gt;</td><td><a id="sa_t"/>
        <p>Is the size specifier, 
      encoded in
      <q>imm13&lt;12&gt;:imm13&lt;5:0&gt;</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">imm13&lt;12&gt;</th>
                <th class="bitfield">imm13&lt;5:0&gt;</th>
                <th class="symbol">&lt;T&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0</td>
                <td class="bitfield">0xxxxx</td>
                <td class="symbol">S</td>
              </tr>
              <tr>
                <td class="bitfield">0</td>
                <td class="bitfield">10xxxx</td>
                <td class="symbol">H</td>
              </tr>
              <tr>
                <td class="bitfield">0</td>
                <td class="bitfield">110xxx</td>
                <td class="symbol">B</td>
              </tr>
              <tr>
                <td class="bitfield">0</td>
                <td class="bitfield">1110xx</td>
                <td class="symbol">B</td>
              </tr>
              <tr>
                <td class="bitfield">0</td>
                <td class="bitfield">11110x</td>
                <td class="symbol">B</td>
              </tr>
              <tr>
                <td class="bitfield">0</td>
                <td class="bitfield">111110</td>
                <td class="symbol">RESERVED</td>
              </tr>
              <tr>
                <td class="bitfield">0</td>
                <td class="bitfield">111111</td>
                <td class="symbol">RESERVED</td>
              </tr>
              <tr>
                <td class="bitfield">1</td>
                <td class="bitfield">xxxxxx</td>
                <td class="symbol">D</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;const&gt;</td><td><a id="sa_const"/>
        
          <p class="aml">Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits, encoded in the "imm13" field.</p>
        
      </td></tr></table></div><div class="syntax-notes"/><div class="alias_ps_section"><h3 class="pseudocode">Operation</h3><p>The description of <a href="eor_z_zi.html">EOR (immediate)</a> gives the operational pseudocode for this instruction.</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
              <ul><li>
              The values of the data supplied in any of its registers.
            </li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
              <ul><li>
              The values of the data supplied in any of its registers.
            </li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
          This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
        </p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
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      This document is Non-Confidential.
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